Semiconductor memories are commonly randomly accessible. This means that a user must provide an address for each element accessed in a memory array. Some memories, such as SAMs, are sequentially accessed. This means that a clock pulse is provided to the SAM, and elements within a predetermined block within the array are sequentially accessed, one element per pulse. This is used with advantage in devices such as dual-port and triple-port RAMs (random access memories), which have both sequential and random access ports.
A well known way to accomplish sequential access is illustrated in FIG. 1. Clock 10 pulses counter 11, which increments by calculating its next output by using feedback from its present output. Counter 11 outputs an address to predecoder 12, which outputs the address predecoded to decode stage 13, which then presents the address fully decoded to array 14. Predecoder 12 and decode stage 13 work together to efficiently access an element in array 14 which corresponds to the address output of counter 10. As clock 10 pulses, counter 11 counts, and elements in array 14 are sequentially accessed. Often counter 11 is presettable, allowing the sequential access to begin at a predetermined element within array 14.
It would be advantageous to combine a counter and a predecoder into a single stage, thus reducing design complexity and size.
It would also be advantageous if the predecoded counter was presettable, allowing sequential access to begin at any predetermined element within a memory array.
It would further be advantageous if the predecoded counter were synchronous. The outputs of the predecoded counter would then change simultaneously, thus avoiding spurious activation of one or more outputs.